The Rambus DDR3 memory interface solution is a high-performance, low-cost PHY tailored for consumer electronics. Rambus' consumer DDR3 PHY solution is capable of supporting data rates of up to 1600 megatransfers per second (MT/s) in a low-cost wire bond package. It incorporates patented innovations such as on-chip Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), FlexPhase™ Timing Adjustment circuits, Output Driver Calibration, and On Die Termination (ODT) Calibration to provide a complete memory solution. The PHY also provides backwards compatibility for DDR2 SDRAM applications.
The DDR3 PHY consists of a Command/Address (C/A) macro cell and a variable number of 8-bit Data macro cells. The PHY contains all of the necessary components for robust operation including IO pads, PLL, Power Mode Management (PMM), transmit and receive paths, clock distribution, control logic, power distribution and electrostatic discharge (ESD) protection circuitry.
Rambus FlexPhase technology is employed to provide for optimum memory system timing, including write-leveling and read-leveling delay adjustment for fly-by topologies. Support is provided for the standard DDR3 write-leveling calibration process performed by the memory controller.
Rambus offers its DDR3 PHY in a PHY development package (PDP) which allows memory interface designers to customize their DDR3 implementation to meet their specific application needs. Through the PDP, Rambus provides all the necessary building blocks including the PHY architecture, schematics, models, generic layout, floor plan, verification IP, implementation documentation, testing documentation, design scripts and simulation files to ensure interface design success.
- 800 to 1600MT/s data rates
- DDR3 and DDR2 signaling modes: SSTL_1.35, SSTL_1.5, and SSTL_1.8 logic levels
- FlexPhase™ timing adjustment of data, address and clock signals
- Programmable output impedance and on-die termination
- ZQ calibration of output impedance and on-die calibration
- Integrated DLL for ASIC interface and high-performance PLL for interface and device clock synthesis
- Synchronous ASIC interface for compatibility with synthesizable design flows
- Programmable output slew rate
- Power mode management module
- In-PHY characterization module
- Support for wire bond or flip-chip packages